A) Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC) device to be used with a portable equipment and the like, and more particularly to a semiconductor device aiming at suppressing a power source voltage fluctuation and unnecessary radiation.
B) Description of the Related Art
As shown in FIG. 4A, when a semiconductor integrated circuit (IC) package 110 is mounted on a printed circuit board 120 or the like and used with other circuits, a bypass capacitor 103 of about 1 μF is externally connected between a lead 101 for a package power source voltage and a ground plane 102 of the printed circuit board to suppress a fluctuation of the voltage to be supplied to IC. In the IC package 110, a power source voltage pad 107 on a silicon chip 130 is connected by a bonding wire to the package power source voltage lead 101. An internal circuit of IC is connected to the bypass capacitor 103 via the pad 107, bonding wire 105 and lead 101.
The bypass capacitor externally connected to IC and a noise cancelling circuit for signal lines can suppress to some degree a power source voltage fluctuation outside IC and noises on signal lines. However, it is difficult to perfectly prevent a power source voltage fluctuation inside IC and malfunctions and noises of the IC internal circuits by the external electrostatic discharge etc. In the following, a mechanism of a power source voltage fluctuation inside IC will be considered.
As shown in FIG. 4B, when a change ΔI in a current I occurs, a potential (power source voltage) of power source lines VDD and VSS having a wiring resistance R changes by ΔV=ΔI*R, where the current I flows when a signal rises or falls and a total capacitance C is charged or discharged. The capacitance C includes a wiring capacitance, a transistor gate capacitance and a transistor junction capacitance. This change in the power source potential becomes power source noises and has the influence upon a frequency band several hundred to several thousand times the frequency of a clock signal (internal circuit operation frequency).
As shown in FIG. 4C, the bypass capacitor 103 is connected to IC via the lead 101 and bonding wire 105. The lead 101 and bonding wire 105 have an equivalent inductance component L and reactance component RC. In the high frequency band, the inductance component L is dominant resulting in a high impedance. The bypass capacitor 103 externally connected to IC and the inside of IC are separated by the inductance L in the high frequency band. Power source noises generated by the operation of internal circuits of IC are hard to be sufficiently absorbed by the bypass capacitor. Power source noises generated inside IC leak to the external from signal input/output pads so that IC becomes a high frequency noise source.
Power source noises generated inside IC influence the operation of functional blocks constituting IC and each functional block operates erroneously in some cases. In an IC having both analog and digital circuits among other IC's, power source noises generated by a switching operation of digital circuits influence the operation of analog circuits. This inevitably leads to the deteriorated IC characteristics. It is desired to suppress a fluctuation of a power source voltage inside IC.
Japanese Patent Laid-open Publication No. SHO-60-161655 has proposed that a power source line in IC is used as one electrode and a substrate area along this power source line is used as the other electrode to form a capacitor between the positive and negative power source lines, this capacitor constituting a portion of a bypass capacitor. According to this proposed device, the bypass capacitor can be formed directly between the power source lines inside IC so that a power source voltage fluctuation can be suppressed a little. Capacitance capable of being built in IC by this method has a limit of probably about several hundred pF. Since the total capacitance inside IC (all gate capacitances, all junction capacitances and all wiring capacitances) is several thousand to several ten thousand pF, it is difficult to sufficiently absorb power source noises.
Japanese Patent Laid-open Publication No. HEI-2-202051, Japanese Patent Laid-open Publication No. HEI-10-326868 and Japanese Patent Laid-open Publication No. HEI-10-150148 describe also techniques of forming a capacitance for suppressing a power source fluctuation inside IC. The techniques described in these documents are also hard to form a sufficient capacitance inside IC.